? semiconductor components industries, llc, 2003 january, 2003 ? rev. 10 353 publication order number: mc74hct373a/d mc74hct373a octal 3-state noninverting transparent latch with lsttl-compatible inputs high?performance silicon?gate cmos the mc74hct373a may be used as a level converter for interfacing ttl or nmos outputs to high?speed cmos inputs. the hct373a is identical in pinout to the ls373. the eight latches of the hct373a are transparent d?type latches. while the latch enable is high the q outputs follow the data inputs. when latch enable is taken low, data meeting the setup and hold times becomes latched. the output enable does not affect the state of the latch, but when output enable is high, all outputs are forced to the high?impedance state. thus, data may be latched even when the outputs are not enabled. the hct373a is identical in function to the hct573a, which has the input pins on the opposite side of the package from the output pins. this device is similar in function to the hct533a, which has inverting outputs. ? output drive capability: 15 lsttl loads ? ttl/nmos?compatible input levels ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 4.5 to 5.5 v ? low input current: 1.0 a ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 196 fets or 49 equivalent gates marking diagrams 1 20 a = assembly location wl = wafer lot yy = year ww = work week soic wide?20 dw suffix case 751d hct373a awlyyww pdip?20 n suffix case 738 1 20 mc74hct373an awlyyww tssop?20 dt suffix case 948e 1 20 1 20 1 20 device package shipping ordering information mc74hct373an pdip?20 1440 / box mc74hct373adw soic?wide 38 / rail mc74hct373adwr2 soic?wide 1000 / reel mc74hct373adt tssop?20 75 / rail mc74hct373adtr2 tssop?20 2500 / reel hct 373a alyw 1 20 http://onsemi.com
mc74hct373a http://onsemi.com 354 logic diagram data inputs d0 d1 d2 d3 d4 d5 d6 d7 18 17 14 13 8 7 4 3 1 output enable 19 q0 q1 q2 q3 q4 q5 q6 q7 16 15 12 9 6 5 2 pin 20 = v cc pin 10 = gnd noninverting outputs 11 latch enable pin assignment q2 d1 d0 q0 output enable gnd q3 d3 d2 q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 q6 d6 d7 q7 v cc latch enable q4 d4 d5 q5 function table inputs output output latch enable enable d q lhhh lhll l l x no change hxxz x = don't care z = high impedance ??????????? ? ????????? ? ??????????? design criteria ???? ? ?? ? ???? value ??? ? ? ? ??? units ??????????? ??????????? internal gate count* ???? ???? 49 ??? ??? ea. ??????????? ??????????? internal gate propagation delay ???? ???? 1.5 ??? ??? ns ??????????? ? ????????? ? ??????????? internal gate power dissipation ???? ? ?? ? ???? 5.0 ??? ? ? ? ??? w ??????????? ??????????? speed power product ???? ???? 0.0075 ??? ??? pj ???????????????? ???????????????? *equivalent to a two-input nand gate.
mc74hct373a http://onsemi.com 355 ??????????????????????? ??????????????????????? maximum ratings* ???? ???? symbol ?????????????? ?????????????? parameter ????? ????? value ??? ??? unit ???? ???? v cc ?????????????? ?????????????? dc supply voltage (referenced to gnd) ????? ????? 0.5 to + 7.0 ??? ??? v ???? ???? v in ?????????????? ?????????????? dc input voltage (referenced to gnd) ????? ????? 0.5 to v cc + 0.5 ??? ??? v ???? ???? v out ?????????????? ?????????????? dc output voltage (referenced to gnd) ????? ????? 0.5 to v cc + 0.5 ??? ??? v ???? ???? i in ?????????????? ?????????????? dc input current, per pin ????? ????? 20 ??? ??? ma ???? ???? i out ?????????????? ?????????????? dc output current, per pin ????? ????? 35 ??? ??? ma ???? ???? i cc ?????????????? ?????????????? dc supply current, v cc and gnd pins ????? ????? 75 ??? ??? ma ???? ? ?? ? ???? p d ?????????????? ? ???????????? ? ?????????????? power dissipation in still air, plastic dip2 soic package2 tssop package2 ????? ? ??? ? ????? 750 500 450 ??? ? ? ? ??? mw ???? ???? t stg ?????????????? ?????????????? storage temperature ????? ????? 65 to + 150 ??? ??? c ???? ? ?? ? ???? t l ?????????????? ? ???????????? ? ?????????????? lead temperature, 1 mm from case for 10 seconds (plastic dip, soic, ssop or tssop package) ????? ? ??? ? ????? 260 ??? ? ? ? ??? c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. 2derating e plastic dip: 10 mw/ c from 65 to 125 c soic package: 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the on semiconductor high?speed cmos data book (dl129/d). recommended operating conditions ???? ???? symbol ??????????????? ??????????????? parameter ??? ??? min ?? ?? max ??? ??? unit ???? ???? v cc ??????????????? ??????????????? dc supply voltage (referenced to gnd) ??? ??? 4.5 ?? ?? 5.5 ??? ??? v ???? ???? v in , v out ??????????????? ??????????????? dc input voltage, output voltage (referenced to gnd) ??? ??? 0 ?? ?? v cc ??? ??? v ???? ???? t a ??????????????? ??????????????? operating temperature, all package types ??? ??? 55 ?? ?? + 125 ??? ??? c ???? ???? t r , t f ??????????????? ??????????????? input rise and fall time (figure 1) ??? ??? 0 ?? ?? 500 ??? ??? ns dc electrical characteristics (voltages referenced to gnd) ???? ???? ????????? ????????? ????????? ????????? ???? ???? ????????? ????????? guaranteed limit ??? ??? ???? ???? symbol ????????? ????????? parameter ????????? ????????? test conditions ???? ???? v cc v ???? ???? 55 to 25 c ??? ??? 85 c ???? ???? 125 c ??? ??? unit ???? ? ?? ? ???? v ih ????????? ? ??????? ? ????????? minimum high?level input voltage ????????? ? ??????? ? ????????? v out = 0.1 v or v cc 0.1 v |i out | 20 a ???? ? ?? ? ???? 4.5 5.5 ???? ? ?? ? ???? 2.0 2.0 ??? ? ? ? ??? 2.0 2.0 ???? ? ?? ? ???? 2.0 2.0 ??? ? ? ? ??? v ???? ? ?? ? ???? v il ????????? ? ??????? ? ????????? maximum low?level input voltage ????????? ? ??????? ? ????????? v out = 0.1 v or v cc 0.1 v |i out | 20 a ???? ? ?? ? ???? 4.5 5.5 ???? ? ?? ? ???? 0.8 0.8 ??? ? ? ? ??? 0.8 0.8 ???? ? ?? ? ???? 0.8 0.8 ??? ? ? ? ??? v ???? ???? v oh ????????? ????????? minimum high-level output voltage ????????? ????????? v in = v ih or v il |i out | 20 a ???? ???? 4.5 5.5 ???? ???? 4.4 5.4 ??? ??? 4.4 5.4 ???? ???? 4.4 5.4 ??? ??? v ???? ? ?? ? ???? ????????? ? ??????? ? ????????? ????????? ? ??????? ? ????????? v in = v ih or v il |i out | 6.0 ma ???? ? ?? ? ???? 4.5 ???? ? ?? ? ???? 3.98 ??? ? ? ? ??? 3.84 ???? ? ?? ? ???? 3.7 ??? ? ? ? ??? ???? ???? v ol ????????? ????????? maximum low-level output voltage ????????? ????????? v in = v ih or v il |i out | 20 a ???? ???? 4.5 5.5 ???? ???? 0.1 0.1 ??? ??? 0.1 0.1 ???? ???? 0.1 0.1 ??? ??? v ???? ? ?? ? ???? ????????? ? ??????? ? ????????? ????????? ? ??????? ? ????????? v in = v ih or v il |i out | 6.0 ma ???? ? ?? ? ???? 4.5 ???? ? ?? ? ???? 0.26 ??? ? ? ? ??? 0.33 ???? ? ?? ? ???? 0.4 ??? ? ? ? ??? ???? ? ?? ? ???? i in ????????? ? ??????? ? ????????? maximum input leakage cur- rent ????????? ? ??????? ? ????????? v in = v cc or gnd ???? ? ?? ? ???? 5.5 ???? ? ?? ? ???? 0.1 ??? ? ? ? ??? 1.0 ???? ? ?? ? ???? 1.0 ??? ? ? ? ??? a ???? ? ?? ? ???? i oz ????????? ? ??????? ? ????????? maximum three?state leakage current ????????? ? ??????? ? ????????? output in high?impedance state v in = v il or v ih v out = v cc or gnd ???? ? ?? ? ???? 5.5 ???? ? ?? ? ???? 0.5 ??? ? ? ? ??? 5.0 ???? ? ?? ? ???? 10 ??? ? ? ? ??? a ???? ???? i cc ????????? ????????? maximum quiescent supply current (per package) ????????? ????????? v in = v cc or gnd i out = 0 a ???? ???? 5.5 ???? ???? 4.0 ??? ??? 40 ???? ???? 160 ??? ??? a this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hct373a http://onsemi.com 356 ???? ???? i cc ????????? ????????? additional quiescent supply current ????????? ????????? v in = 2.4 v, any one input v in =v cc or gnd other in p uts ???? ???? 5.5 ????? ????? ?55 c ????? ????? 25 c to 125 c ??? ??? ma ???? ???? ????????? ????????? c urren t ????????? ????????? v in = v cc or gnd , oth er i npu t s l out = 0 a ???? ???? ????? ????? 2.9 ????? ????? 2.4 ??? ??? note: 1. total supply current = i cc + i cc . note: information on typical parametric values can be found in chapter 2 of the on semiconductor high?speed cmos data book (dl129/d). ac electrical characteristics (v cc = 5.0 v 10%, c l = 50 pf, input t r = t f = 6.0 ns) ????? ????? ?????????????????? ?????????????????? ?????????? ?????????? guaranteed limit ??? ??? ????? ? ??? ? ????? symbol ?????????????????? ? ???????????????? ? ?????????????????? parameter ???? ? ?? ? ???? 55 to 25 c ???? ? ?? ? ???? 85 c ???? ? ?? ? ???? 125 c ??? ? ? ? ??? unit ????? ????? t plh , t phl ?????????????????? ?????????????????? maximum propagation delay, input d to q (figures 1 and 5) ???? ???? 28 ???? ???? 35 ???? ???? 42 ??? ??? ns ????? ? ??? ? ????? t plh , t phl ?????????????????? ? ???????????????? ? ?????????????????? maximum propagation delay, latch enable to q (figures 2 and 5) ???? ? ?? ? ???? 32 ???? ? ?? ? ???? 40 ???? ? ?? ? ???? 48 ??? ? ? ? ??? ns ????? ????? t plz , t phz ?????????????????? ?????????????????? maximum propagation delay, output enable to q (figures 3 and 6) ???? ???? 30 ???? ???? 38 ???? ???? 45 ??? ??? ns ????? ? ??? ? ????? t pzl , t pzh ?????????????????? ? ???????????????? ? ?????????????????? maximum propagation delay, output enable to q (figures 3 and 6) ???? ? ?? ? ???? 35 ???? ? ?? ? ???? 44 ???? ? ?? ? ???? 53 ??? ? ? ? ??? ns ????? ? ??? ? ????? t tlh , t thl ?????????????????? ? ???????????????? ? ?????????????????? maximum output transition time, any output (figures 1 and 5) ???? ? ?? ? ???? 12 ???? ? ?? ? ???? 15 ???? ? ?? ? ???? 18 ??? ? ? ? ??? ns ????? ????? c in ?????????????????? ?????????????????? maximum input capacitance ???? ???? 10 ???? ???? 10 ???? ???? 10 ??? ??? pf ????? ????? c out ?????????????????? ?????????????????? maximum three-state output capacitance (output in high-impedance state) ???? ???? 15 ???? ???? 15 ???? ???? 15 ??? ??? pf note: for propagation delays with loads other than 50 pf, and information on typical parametric values, see chapter 2 of the on semiconductor high-speed cmos data book (dl129/d). typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance (per latch)* 65 pf * used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the on semiconductor high?speed cmos data book (dl129/d). timing requirements (v cc = 5.0 v 10%, input t r = t f = 6.0 ns) ????? ????? ?????????????????? ?????????????????? ?????????? ?????????? guaranteed limit ??? ??? ????? ? ??? ? ????? symbol ?????????????????? ? ???????????????? ? ?????????????????? parameter ???? ? ?? ? ???? 55 to 25 c ???? ? ?? ? ???? 85 c ???? ? ?? ? ???? 125 c ??? ? ? ? ??? unit ????? ? ??? ? ????? t su ?????????????????? ? ???????????????? ? ?????????????????? minimum setup time, input d to latch enable (figure 4) ???? ? ?? ? ???? 10 ???? ? ?? ? ???? 13 ???? ? ?? ? ???? 15 ??? ? ? ? ??? ns ????? ????? t h ?????????????????? ?????????????????? minimum hold time, latch enable to input d (figure 4) ???? ???? 10 ???? ???? 13 ???? ???? 15 ??? ??? ns ????? ? ??? ? ????? t w ?????????????????? ? ???????????????? ? ?????????????????? minimum pulse width, latch enable (figure 2) ???? ? ?? ? ???? 12 ???? ? ?? ? ???? 15 ???? ? ?? ? ???? 18 ??? ? ? ? ??? ns ????? ? ??? ? ????? t r , t f ?????????????????? ? ???????????????? ? ?????????????????? maximum input rise and fall times (figure 1) ???? ? ?? ? ???? 500 ???? ? ?? ? ???? 500 ???? ? ?? ? ???? 500 ??? ? ? ? ??? ns
mc74hct373a http://onsemi.com 357 expanded logic diagram d0 3 dq le 2 q0 11 1 latch enable output enable d1 4 dq le 5 q1 d2 7 dq le 6 q2 d3 8 dq le 9 q3 d4 13 dq le 12 q4 d5 14 dq le 15 q5 d6 17 dq le 16 q6 d7 18 dq le 19 q7 switching waveforms figure 1. figure 2. 3 v gnd t f t r input d q 0.3 v 1.3 v 2.7 v 10% 1.3 v 90% t tlh t plh t phl t thl 3 v gnd 1.3 v latch enable t plh t phl q t w 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v q t pzl t plz t pzh t phz 10% 90% 3 v gnd high impedance v ol v oh high impedance figure 3. figure 4. q output enable 1.3 v input d latch enable 3 v 3 v gnd gnd valid t h t su 1.3 v
mc74hct373a http://onsemi.com 358 *includes all probe and jig capacitance c l * test point device under test output figure 5. figure 6. *includes all probe and jig capacitance c l * test point device under test output connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k test circuits
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